The present invention relates generally to electronic circuits, and, more particularly, to a system for testing an integrated circuit.
Integrated circuits (ICs) today can include up to a billion electronic components on a single chip. With such complex circuitry, a lot of testing must be performed to insure the circuit will operate as proposed. For example, functional simulation is performed on the circuit design before the circuit is fabricated, and on the circuit itself after fabrication. After fabrication, the circuit or chip must also be tested for manufacturing defects. Manufacturing test is performed using automated test equipment (ATE) and an IC being testing is referred to as a device under test (DUT). The ATE includes a processor, a digital signal processor (DSP), a probe head, and a probe card. The processor executes a test program corresponding to the manufacturing test. The DSP is used to conduct analog testing of the DUT. The probe head connects the ATE to the DUT. Generally, a pogo pin is used as the probe head. The pogo pin connects the ATE to contact test points and component leads of the DUT. The probe card is an electrical interface, such as a printed circuit board (PCB) on which the DUT is mounted. The ATE includes multiple pogo pins in the form of a bed of pogo pins. Multiple ICs are connected to the ATE using the bed for simultaneous manufacturing testing.
The pogo pin is rated for testing up to a million DUTs before being replaced and is generally made of gold. The pogo pin is highly conductive and conducts a large current, which causes it to become resistive over time. The resistance of the pogo pin results in development of a potential drop across the pogo pin that can result in erroneous feedback from the manufacturing tests performed on the DUT, leading to an increase in yield loss, i.e., some good chips may be rejected. One solution to reduce this yield loss is to replace the pogo pins after a few thousand DUTs are tested. However, replacement of the pogo pins is a manual and time-consuming process that results in increased manufacturing test time and consequently in increased manufacturing cost.
During the manufacturing test, all circuits of the DUT are tested. The chip is scribed as good if all of the internal circuits pass the manufacturing test; while the chip is scribed as bad if even a single internal circuit fails.
When testing an Analog-to-Digital Converter (ADC), the ADC receives an analog voltage signal (Vin) in a defined range and generates a digital signal. The ADC also receives high and low reference voltage signals, Vrefh and Vrefl respectively, which determine the range of analog voltage signals (Vin) that the ADC can convert to digital signals. For example, a 2-bit ADC has Vrefh=4 volts (V) and Vrefl=0V. The 2-bit ADC can convert the analog voltage signals (Vin) ranging from 0V to 4V. This range of voltages is divided into steps and a size of each step is determined by the following formula:Step Size=(Vrefh−Vrefl)/2^N, where N represents number of bits in the digital signal.In this example, the step size of the ADC is 1V, which corresponds to one least significant bit (LSB). Thus, the reference voltage signals determine the digital signal output by the ADC. An anomaly in the reference voltage signal adversely affects the digital signal.
The ADC has two reference pins for the high and low reference voltage signals. Usually these reference pins are connected to a supply pin of the ADC. The pogo pins of the ATE are connected to the reference pins of the ADC to perform the manufacturing test on the ADC. The reference pins of the ADC draw less current from the ATE than the supply pin. When the supply and reference pins are connected to each other, a large current flows by way of the reference pins, resulting in an anomaly of the potential at the reference pins. Thus, for a 2-bit ADC, the high reference voltage signal (Vrefh) goes down from 4V to 3.5V, while the low reference voltage signal (Vrefl) increases from 0V to 0.5V. This changes the step size from 1V to 0.75V, which is undesirable. A total unadjusted error (TUE) of the ADC represents a difference between an ideal digital signal and the actual digital signal output by the ADC. In this example, the TUE calculated by the ATE is high and results in the ADC failing the manufacturing test. Thus, the ADC fails the manufacturing test due to an error in the pogo pin and not because of an actual manufacturing defect. Such a scenario leads to increased yield loss, which in turn results in increased manufacturing costs.
To overcome the above-mentioned problem, the reference voltage signals received by the reference pins of the ADC by way of the pogo pins are exposed to an alternate pair of pins of the ADC. The reference voltage signals are measured from the alternate reference pins by way of an analog circuit. A software calibration method implemented by the ATE adjusts the measured reference voltage signals such that the ADC passes the manufacturing test. However, this solution involves the use of an additional pair of pins, an additional analog circuit, and a software calibration code. The addition of two extra pins on each ADC, and hence on each DUT, limits the total number of DUTs that can be tested in parallel by the ATE. Moreover, the additional analog circuit results in area overhead of the DUT.
Therefore, it would be advantageous to be able to accurately test an IC and avoid unnecessary yield loss.